The present invention relates to a process for manufacturing an integrated circuit comprising an array of memory cells, such as for example an array of electrically-programmable non-volatile memory cells (EPROM, Flash EEPROM or EEPROM memory cells).
It is known that most semiconductor memory cells, particularly electrically-programmable non-volatile memory cells, are formed by stacked-gate MOS transistors having a floating gate electrode and a control gate electrode. Typically, the floating gate electrode and the control gate electrode are obtained from two different layers of conductive material, such as polysilicon, isolated by means of a dielectric layer (interpoly dielectric).
An integrated circuit comprising an array of memory cells always comprises several other circuit blocks containing MOSFETs. As known, MOSFETs comprise only one gate electrode, also typically made of polysilicon. For example, row decoder circuits are needed for selecting specific rows of memory cells inside the memory cell array. The drivers of the row decoder circuits must be electrically connected to the rows of the array. Normally, polysilicon strips are used as interconnection lines between the drivers of the row decoder and the rows of the array. The use of polysilicon strips as interconnection lines instead of metal lines is advantageous because in this way it is normally possible to reduce the number of different metal layers to be formed, and the manufacturing processes are consequently greatly simplified.
Known processes for manufacturing integrated circuits comprising an array of memory cells as well as conventional MOSFETs provides for forming, on active areas of a common semiconductor substrate, a gate oxide layer which will form the gate oxide of both the memory cells and the MOSFETs of the circuitry; forming on the whole substrate (and thus also on the gate oxide layer) a first layer of polysilicon, forming over the first polysilicon layer a layer of dielectric material (interpoly dielectric); selectively removing the interpoly dielectric in regions of the substrate wherein the MOSFETs of the circuitry are to be formed, thus leaving the interpoly dielectric only in the region of the memory cell array; forming a second layer of polysilicon over the whole substrate, so that in the region of the memory cell array the second polysilicon layer is separated from the first polysilicon layer by the interpoly dielectric, while in the region of the circuitry the second polysilicon layer is directly superimposed over the first polysilicon layer (xe2x80x9cdouble polysilicon in short-circuitxe2x80x9d).
The gate electrodes of the MOSFETs of the circuitry and the control gate electrodes (rows of the memory cell array) are then simultaneously defined.
To this purpose, a first layer of photoresist is deposited over the second layer of polysilicon. The first layer of photoresist is selectively exposed to light by means of a first mask and the first layer of photoresist is selectively removed. The second polysilicon layer is then selectively removed where it is not covered by the first photoresist layer. Using an etching process suitable for removing the polysilicon but not the oxide and the interpoly dielectric, in the regions of the substrate dedicated to the circuitry, where the first and second layers of polysilicon are in direct contact, both the second and the first layer of polysilicon are simultaneously etched down to the gate oxide layer; in the region of the substrate dedicated to the memory cell array only the second level of polysilicon is removed down to the interpoly dielectric layer.
Without removing the first layer of photoresist, a second layer of photoresist is deposited over the whole chip. The second layer of photoresist is then selectively exposed to light by means of a second mask, and the second photoresist layer is selectively removed from the region of the chip wherein the memory cell array is to be formed. Thus, the region of the chip dedicated to the circuitry is completely covered by the second layer of photoresist, while in the region for the array only isles of the first photoresist layer (defined by means of the first mask) are left. Then, the interpoly dielectric layer, the first layer of polysilicon and the gate oxide layer are selectively removed to define the floating gates and the gate oxide of the memory cells, i.e. to completely define the rows of the memory cell array.
The use of two layers of photoresist has shown to be critical: during the selective removal of the second layer of photoresist it may happen that portions of the first layer of photoresist in the region of the memory cell array are also removed; if this happens, the silicon wafers are to discarded, with significant impact on the manufacturing yield.
In order to overcome this problems, an alternative process has been proposed that after the second layer of polysilicon has been deposited provides for depositing a first layer of photoresist; selectively removing it from the area of the chip reserved to the circuitry while leaving all the area for the memory cell array covered by the first photoresist layer; etching the second and the first polysilicon layers down to the gate oxide to define the gates of the MOSFETs of the circuitry; completely removing the first photoresist layer; depositing a second photoresist layer; selectively removing the second photoresist layer from the area reserved to the memory cell array while leaving the area for the circuitry covered; and then selectively removing the second layer of polysilicon, the interpoly dielectric, the first layer of polysilicon and the gate oxide layer for defining the rows of the memory cell array and the gates of the memory cells in the memory cell array.
In this process, the photolithographic mask used for selectively removing the first photoresist layer and the photolithographic mask used for selectively removing the second photoresist layer are not overlapping; in other words, all around the memory cell array the second polysilicon layer is completely removed. In this way, however, the rows of the memory cell array and the interconnection lines between the rows and the circuitry, such as the row decoder, both formed in the second layer of polysilicon, are disconnected from each other. It is thus necessary to provide metal jumpers for connecting the ends of the rows of the memory cell array to respective ends of the interconnection lines outside the memory cell array, for example coming from the row decoder. This is disadvantageous, because for each row two contacts are to be provided, so that not only the number of contacts increases enormously (especially for memories of large sizes), but also the provision of contacts does not allow to reduce the spacing between the rows. Additionally, the larger the number of contacts to be provided, the higher the probability of defects, and the resulting manufacturing yield decreases.
In view of the state of the art described, it is an object of the present invention that of providing a process for manufacturing an integrated circuit comprising an array of memory cells suitable for overcoming the drawbacks of the known processes.
According to the invention, such object is attained by means of a process for manufacturing an integrated circuit comprising an array of memory cells, providing for:
a) forming in a memory cell array area of a semiconductor layer an active area for the memory cells;
b) forming over said active area for the memory cells a gate oxide layer;
c) forming over the whole integrated circuit a first layer of conductive material;
d) forming over the first layer of conductive material a layer of insulating material;
e) removing the layer of insulating material from outside the memory cell array area;
f) forming over the whole integrated circuit a second layer of conductive material which in the memory cell array area is separated from the first layer of conductive material by the insulating material layer, while outside the memory cell array area is directly superimposed over said first layer of conductive material;
g) inside the memory cell array area, defining first strips of the second layer of conductive material for forming rows of the memory cell array, and outside the memory cell array area defining second strips of the second layer of conductive material for forming interconnection lines for electrically interconnecting the rows of the memory cell array with a circuitry, said defining the second strips providing for selectively etching the first and second layers of conductive material outside the memory cell array area by means of a first mask, and said defining the first strips providing for selectively etching the second layer of conductive material, the layer of insulating material and the first layer of conductive material inside the memory cell array area by means of a second mask;
characterized in that the first and second masks overlap in a boundary region around the memory cell array area, so that the first strips and the second strips of the second layer of conductive material are automatically joined at respective ends thereof at said boundary region.
Thanks to the present invention, it is possible to form interconnection lines which are automatically joined to the rows of the memory cell array, so that it is not necessary to provide metal jumpers for connecting the interconnection lines to the rows of the memory cell array. Additionally, the process of the invention is not critical because it does not provide for using two superimposed layers of photoresist.